1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor, and a method for manufacturing the same.
2. Related Art
FIG. 13 shows a structure of a Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) disclosed in U.S. Pat. No. 7,268,045 and Japanese Laid-open patent publication NO. 2002-237591. The LDMOS includes a p-type body region 22 formed in a surface of an n-type well 12, an n-type source region 18 formed in the body region 22, and a drain region 16 formed in the surface of the n-type well 12 with an element isolation insulating layer 28 interposed between the body region 22 and the drain region 16. Here, a buried region 30 is formed below the source region 18 in the body region 22.
These patent documents state that the LDMOS has the following problem. When a high voltage is applied, the source region, the body region and the drain region of the LDMOS respectively correspond to an emitter, a base and a collector of a parasitic bipolar transistor, and the parasitic bipolar transistor may be turned on by carriers (holes) created by impact ionization in the drain region of the LDMOS. Once the parasitic bipolar transistor is turned on, continued generation of secondary holes at the drain side will keep the bipolar transistor turned on until the device is destroyed. When a secondary hole current turns on a parasitic NPN device, this device begins to provide a secondary electron current. If the ratio of secondary electrons per secondary hole times the ratio of secondary holes per electron exceeds 1, the secondary electron current and secondary hole current are in a positive feedback relationship, and the device is no longer controlled by the gate.
In addition, the above-mentioned patent documents state that generation of the secondary electrons can be considerably reduced by providing the buried region 30 and providing a low resistance shunt path for the holes that are generated in the drain region due to impact ionization, thereby decreasing the gain of the parasitic PNP bipolar transistor and increasing the safe operating area (SOA).
In addition, among high breakdown voltage MOS transistors, there has been known a so-called LOCOS offset type structure with a thick field oxide layer (hereinafter referred to as LOCOS) formed at an end of a gate electrode or between the gate electrode, a drain diffusion layer and a source diffusion layer (Japanese Laid-open patent publication NO. 2001-94103).
FIG. 14 shows an example of a semiconductor device with such a structure. A semiconductor device 300 includes a p-type lightly-doped substrate 302, an n-type drain-side diffusion region 312 and an n-type source-side diffusion region 314 formed over the substrate 302, a source electrode 320 formed in a surface of the n-type source-side diffusion region 314, a drain electrode 318 formed in a surface of the n-type drain-side diffusion region 312, a gate insulating layer 336 and a gate electrode 338 formed over a region between the n-type drain-side diffusion region 312 and the n-type source-side diffusion region 314 in the surface of the substrate 302. A channel region is formed between the n-type drain-side diffusion region 312 and the n-type source-side diffusion region 314. In addition, an element isolation insulating layer 332 is provided between the channel region and the drain electrode 318 to isolate them from each other. In addition, an element isolation insulating layer 334 is provided between the channel region and the source electrode 320 to isolate them from each other. With this configuration, the p-type low concentration region constituted by the substrate 302 is provided over the entire lower side of the n-type drain-side diffusion region 312 and the n-type source-side diffusion region 314, and is in contact with the n-type drain-side diffusion region 312 and the n-type source-side diffusion region 314.